A new top-level component, gr-gpio, has recently been merged into the
trunk.
gr-gpio is an extension to the normal USRP firmware, implemented as an
alternative FPGA bitstream, using the exising USRP host code. With the
gr-gpio component you can transmit and receive a digital stream to and
from the USRP which is aligned with the existing analog stream.
Digital data is sent to or received from the daughterboard GPIO pins
and sacrifice one bit each from the I and the Q analog streams to
transport the digital bits.
Receiving Streaming Digital Samples ¶
Digital streams are sampled from GPIO 14 and GPIO 15 from the selected
daughterboard and replace the LSB of the I and Q analog streams,
respectively. In the host, on can then use usrp.source_s() to obtain
the combined streams and seperate them with logical bit operations.
The GPIO pins are sampled at the decimated RF rate; that is, the GPIO
data replaces the LSBs at the output of the digital downconverter. As
a result of pipeline delays in the analog processing stream, there
will be a fixed but decimation rate dependent delta between the analog
and digital streams.
Transmitting Streaming Digital Samples ¶
In the host, one uses usrp.sink_s() and encodes the desired digital
data into the LSBs of the I and Q sample data. These are then routed
to GPIO 14 and GPIO 15 of the selected daughterboard. The data is
output on the GPIO pins at the same rate as the sample data arriving
over the USB. Due to pipeline delays in the analog processing stream,
there will be a fixed but interpolation rate dependent delta between
the analog and digital streams.
Full documentation is available at:
http://gnuradio.org/trac/wiki/CompGrGpio
–
Johnathan C.
Corgan Enterprises LLC
http://corganenterprises.com/