Transmitting additional data from N210 to the PC

GNU Radio
1

Hi,

I want to change my USRP N210 - FPGA config to calculate a correlation
sum and transmit this sum synchronously with the I/Q sample pairs to the
PC (e.g to get this samples from an extra channel on the UHD block).
What would be the easiest way to transmit these additional data to the
samples and where are changes necessary (firmware, fpga-config)?

Thanks,

Eral

2

On 09/04/2011 11:18 PM, Eral Tuerkyilmaz wrote:

Hi,

I want to change my USRP N210 - FPGA config to calculate a correlation
sum and transmit this sum synchronously with the I/Q sample pairs to the
PC (e.g to get this samples from an extra channel on the UHD block).
What would be the easiest way to transmit these additional data to the
samples and where are changes necessary (firmware, fpga-config)?

You may want to replace the second DSP in the top level verilog with
your own module. On the host side, just configure the uhd source block
for two channels.

-josh

3

Hello,

Thanks for your suggestion. I tried to replace the second DSP Core by a
simple counter so that i should receive something on the second channel.

Then instatiated a UHD source block in GRC, added a second channel (Num
Channels = 2) to the UHD Source block and configured it the same way as
the other channel. Then I tried to run the graph but it keeps telling me
that the configuration of the the second channel is wrong (e.g:
uhd_usrp_source_0.set_center_freq(10000000, 1) leads to
vector::_M_range_check … Maybe I’m just using wrong parameters for the
second channel?)

By the way: I’m using a WBX board to get the I/Q Samples. Are there
maybe any other parameters for the USRP board necessary (subdev specs?)
to get this additional samples?

Thank you,
Eral

On 05/09/2011 09:55, Josh B. wrote:

You may want to replace the second DSP in the top level verilog with
your own module. On the host side, just configure the uhd source block
for two channels.

On 09/04/2011 11:18 PM, Eral Tuerkyilmaz wrote:

Hi,

I want to change my USRP N210 - FPGA config to calculate a
correlation

sum and transmit this sum synchronously with the I/Q sample pairs to
the

PC (e.g to get this samples from an extra channel on the UHD block).
What would be the easiest way to transmit these additional data to
the

samples and where are changes necessary (firmware, fpga-config)?

4

Hi all,
I would like to stream floating point numbers from another application
into GRC;
currently sending them over UDP as char arrays, which I was hoping to
convert back into floats in GRC.

Seems like kind of a basic thing, but I can’t get my head around how
this is possible.
Any pointers / advice would be greatly appreciated

Cheers,
Mark

–
mark.cetilia.org | mem1.com | reduxproject.com

5

Marcus ,

Sorry to hijack the post , why is the telescope on 1420 MHz ?

I saw this on your website

Sent from my iPhone
Andrew R.

6

I’m producing the stream in C++ (using openFrameworks) and sending the
data as char arrays,
and have confirmed that this is indeed all that is being sent (e.g.
“1.25”)

I think what I’m missing is how to unpack them from the char arrays in
GRC,
tried various conversions, (“Packed to Unpacked,” “Char to Float,” etc.)
but am just not getting my head around how GRC would handle this

Cheers,
Mark

–
mark.cetilia.org | mem1.com | reduxproject.com

7

On 09/13/2011 07:48 AM, Eral Tuerkyilmaz wrote:

vector::_M_range_check … Maybe I’m just using wrong parameters for the
second channel?)

Yea, it needs a subdev spec to map the wbx frontend to DSP0 and DSP1,
try “A:0 A:0” for the string representation.

-josh

8

On 09/13/2011 07:05 PM, Mark C. wrote:

How are you producing the UDP stream? ARe you saying that in your
“producer” you don’t know how to pack complex-floats into
a UDP buffer, or something else?

The UDP source in GRC is perfectly happy to unpack complex-floats (or
floats, or whatever) from a UDP-based stream.

–
Marcus L.
Principal Investigator
Shirleys Bay Radio Astronomy Consortium

9

Thanks so much Marcus, this makes perfect sense

Cheers,
Mark

–
mark.cetilia.org | mem1.com | reduxproject.com

10

I’m producing the stream in C++ (using openFrameworks) and sending the data as
char arrays,
and have confirmed that this is indeed all that is being sent (e.g. “1.25”)
So, you’re sending them in ASCII? As ASCII strings?

GRC/gnuradio has no method for dealing with that. The UDP block assumes
native machine-binary format for data coming in
over UDP. Doing it in ASCII (Or Unicode, or whatever) strings will
be hugely inefficient, both in terms of bandwidth required–
it takes many more bytes to represent a floating-point number in
ASCII, than in the native binary format, and converting from
strings back into the native binary format is also quite expensive.
Since UDP is entirely binary transparent, there’s no reason
to send them as ascii strings. The only thing you have to watch out
for is if the raw floating-point format between your two
machines is different. But between x86-family machines, it’s all the
same.

–
Marcus L.
Principal Investigator
Shirleys Bay Radio Astronomy Consortium

11

Ok so I have made some headway & am now sending floats over UDP as
binary data (4 bytes),
followed by a null packet (1 byte of “\0”) but am not sure how to unpack
the data into a float in GRC
It’s all happening within the same machine on an Intel Mac so there
shouldn’t be any issues with endianness.
Any ideas / suggestions?

Cheers,
Mark

–
mark.cetilia.org | mem1.com | reduxproject.com

12

Hello,

I tried to change the FPGA design using the new (N2x0 rev3) as template
by simply letting the strobe and sample output of the dsp_core_rx1 open
and assigning them to fixed values:

----- (file: u2plus_core.v) ------------
dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
(.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),.sample(
), .run(run_rx1_d1), .strobe( ), .debug() );

assign sample_rx1 = 32’hDEAD_BEEF;
assign strobe_rx1 = 1;

But it looks like this is taking hours (~2hrs) to compile the FPGA
design (especially Place and Route is taking really long). (I’m using
xilinx ise 13.1)
When I used the original design (with strobe_rx1 and sample_rx1 attached
to the dsp_core_rx1) it compiled much much faster.

After I finally got the output bin file I burned it into the SPI flash
and the device booted fine. Then in GRC I tried to attach both channels
to a File Sink using the USRP subdev specification you suggested me
(thank you for that). It looks like nothing is coming out of both
channels the sink output filesize remains zero bytes.

Is there maybe anything i have overlooked when I was changing the FPGA
design?

Best Regards,
Eral