Dear all,
-
I have resynthesized USRP2 verilog code and generated its bit stream.
I’m using ISE10.1 (with latest service pack). For top level module, I
use u2_rev3.v and u2_core_udp.v are used. And bit file generated has
size of 937kByte. But that size is different from “UDP fpga image (about
841kB)” available at
“http://code.ettus.com/redmine/ettus/projects/public/wiki/U2binaries”.
Please advice to me. -
And for FPGA firmware, i’m quite confused. Because there are many
available firmware images. Which one should i use (name with UDP)??
PN