USRP2 FPGA - Too many BRAMs during MAP in ISE 11.1

GNU Radio
1

Hello,

I am trying to implement the USRP2 FPGA HDL using Xilinx ISE 11.1. I
have
set-up the file structure and the project options per the makefile for
U2_rev3. It will synthesize and translate (39 BRAM) but fails map with
44BRAM. The BRAM usage at map failure is:

Module BRAM Full Hierarchical Name
buffer_pool 8/8 u2_rev3/u2_core/buffer_pool
regf 3/3 u2_rev3/u2_core/aeMB/aeMB_edk32/regf
ram 2/2
u2_rev3/u2_core/mac_rxfifo_int/mac_rx_longfifo/longfifo/ram
ram 2/2 u2_rev3/u2_core/rx_control/rxfifo/longfifo/ram
icache 2/2 u2_rev3/u2_core/sys_ram/icache
ram 2/2 u2_rev3/u2_core/tx_control/txctrlfifo/longfifo/ram
sys_ram 16/16 u2_rev3/u2_core/sys_ram/sys_ram
v2_noinit.ram 1/1
u2_rev3/u2_core/MAC_top/U_MAC_rx/U_MAC_rx_FF/mac_rx_ff_core/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram
v2_noinit.ram 1/1
u2_rev3/u2_core/MAC_top/U_MAC_rx/U_MAC_rx_FF/mac_rx_ff_core/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v2_noinit.ram
v2_noinit.ram 1/1
u2_rev3/u2_core/MAC_top/U_MAC_rx/U_MAC_rx_FF/mac_rx_ff_core/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r/v2_noinit.ram
v2_noinit.ram 1/1
u2_rev3/u2_core/MAC_top/U_MAC_rx/U_MAC_rx_FF/mac_rx_ff_core/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/v2_noinit.ram
mac_tx_ff_ram 1/1
u2_rev3/u2_core/MAC_top/U_MAC_tx/U_MAC_tx_FF/mac_tx_ff_ram
U_RMON 1/1 u2_rev3/u2_core/MAC_top/U_RMON
v2_noinit.ram 1/1
u2_rev3/u2_core/mac_txfifo_int/mac_tx_fifo_2clk/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram
mac_rx_ff_ram 1/1
u2_rev3/u2_core/serdes/serdes_rx/serdes_rx_fifo/fifo_2clock/mac_rx_ff_ram
ram 1/1
u2_rev3/u2_core/serdes/serdes_tx/serdes_tx_fifo/longfifo/ram

I suspect the v2_noinit.ram but am not sure where I went wrong to end up
with them.

Any help or ideas would be greatly appreciated.

Thanks,

Alan

2

Alan Zubatch wrote:

Hello,

I am trying to implement the USRP2 FPGA HDL using Xilinx ISE 11.1. I have
set-up the file structure and the project options per the makefile for
U2_rev3. It will synthesize and translate (39 BRAM) but fails map with
44BRAM. The BRAM usage at map failure is:

Alan,

I have never seen that problem before, but I use 10.1.03, not 11.1. Are
you just trying to build the SVN release? Are you able to use 10.l
instead of 11.1?

The problem looks like it’s in the Xilinx FIFO core, so maybe if you
rebuild it with coregen from 11.1 it will work better.

Please let me know how it goes, since I have been considering an upgrade
to 11.1 myself.

Thanks,
Matt

3

Thanks,
Matt

Matt,

I’ve managed to come up with ‘a’ solution which involved forcing 11.1 to
use distributed RAM in a few instances. Jonathan was nice enough to
offer
to test my changes before I posted them up as being a useful solution. I
sent him my .bin for testing and am on to my next learning experience.

Thanks,

Alan