USRP2 gigabit ethernet code

GNU Radio
1

Hi there,

I’ve been looking through the USRP2 gigabit ethernet code, and had a few
questions.

I noticed that the code for the USRP2 uses the open source gigabit
ethernet
IP core from opencores.org but that it has an additional “Wishbone
compliant
core host interface” (specifically I’m looking at MAC_top.v ) that isn’t
present in the version available from opencores.org. I’m not terribly
familiar with Wishbone, and I’m having some trouble identifying its role
in
the USRP2 code I’m looking at - I saw that it’s supposed to be a
standard
interface between IP cores. It looks like the Wishbone inputs/outputs
are
tied to the internal signals for the IP core - so is it supposed to be
some
way of defining which registers, etc on the physical hardware get used
for
the registers, etc in the core? If so, does that mean that anyone that
uses
that core needs to use the Wishbone interface?

Thank you!
Jennifer

2

Jennifer Ann Petersen wrote:

terribly familiar with Wishbone, and I’m having some trouble
identifying its role in the USRP2 code I’m looking at - I saw that
it’s supposed to be a standard interface between IP cores. It looks
like the Wishbone inputs/outputs are tied to the internal signals for
the IP core - so is it supposed to be some way of defining which
registers, etc on the physical hardware get used for the registers,
etc in the core? If so, does that mean that anyone that uses that
core needs to use the Wishbone interface?

We use an almost completely rewritten version of the opencores tri-mode
ethernet core. The original simply does not work.

The Wishbone interface is for setting parameters in the core (like
maximum packet size, speed, etc.), and for reading back performance
monitoring counters. The high-speed data does not go through the
wishbone, it goes through the fifo interfaces.

Matt